6th Workshop on Productivity and Performance
Date
August 27, 2013
Location
in conjunction with
Euro-Par 2013 Conference
Aachen, Germany
Overview
Driven by current trends in microprocessor design, the number of processor cores and hardware threads available on modern supercomputers grows rapidly from generation to generation while the amount of memory per core will be decreasing. To keep pace, applications need to harness much higher degrees of parallelism while ensuring efficient use of the underlying computing resources, which can be highly concurrent many core systems or heterogeneous accelerator architectures (or a combination of both). Additionally, applications must adhere to additional constraints, in particular with respect to power consumption (both peak and average power) and resilience.
Writing codes that run correctly and efficiently on such complex systems is extraordinarily challenging. At the same time, applications themselves are becoming more complex as well, which can be seen in emerging scale-bridging applications, the integration of Uncertainty Quantification (UQ), or advances in algorithms. Combined, these trends place higher and higher demands on the application development process and thus require adequate tool support for debugging and performance analysis. The PROPER workshop will serve as a forum to present novel work on scalable methods and tools for high-performance computing. The workshop covers parallel program development and analysis, debugging, correctness checking, and performance measurement and evaluation. Further topics include the integration of tools with compilers and the overall development environment, as well as success stories reporting application performance, scalability, reliability, power and energy optimization, or productivity improvements that have been achieved using tools.
The workshop is supported by the Virtual Institute - High Productivity Supercomputing (VI-HPS), an initiative to promote the development and integration of HPC programming tools.
Workshop Topics
- Tools and tool approaches for parallel program development and analysis
- Infrastructure for building parallel program development and analysis tools
- Correctness checking and program verification
- Performance measurement and evaluation
- Success stories about optimization or parallel scalability achieved using tools
Workshop Program
Session 1: 11:00-12:30 - Welcome and Keynote
Chair: Martin Schulz, LLNL
- Performance productivity challenges and researches
for the future of computing
Victor Lee, Intel (pdf)
Session 2: 14:30-16:00 - Runtime Measurements and Analysis
David Böhme, German Research School for Simulation Sciences
- Data Transfer Requirement Analysis with Bandwidth Curves
Josef Weidendorfer (pdf) - Tracking a Value's Influence on Later Computation
Philip Roth (pdf) - Assessing measurement and analysis performance and scalability of Scalasca
Ilya Zhukov and Brian Wylie (pdf)
Session 3: 16:30-18:00 - Program Analysis and Algorithms
Chair: Brian Wylie, Jülich Supercomputing Center
- Detecting SIMDization Opportunities through Static/Dynamic Dependence Analysis
Olivier Aumage, Denis Barthou, Christopher Haine and Tamara Meunier (pdf) - A High-Level IR Transformation System
Herbert Jordan, Peter Thoman and Thomas Fahringer (pdf) - Implementing a systolic algorithm for QR factorization on multicore clusters with PaRSEC
Guillaume Aupy, Mathieu Faverge, Yves Robert, Jakub Kurzak, Piotr Luszczek and Jack Dongarra (pdf)
Keynote Presentation by Victor Lee, Intel
Over the past few decades, compute performance has been improving steadily due to the advancements in semiconductor manufacturing technology, circuit design and computer architecture. We expect the technology treadmill to continue providing us with innovations that would take us to the Exa-scale computing within this decade. Many technology advances that brought us the performance improvement have also increased the level of complexity programmers must deal with. For example, switching from the single-core processor design to the many-core processor design allows us to circumvent the power density challenge and allows the processor performance to continue to scale; however, this switch also requires developers to explore parallelism in order to harness the available compute capability. Similar trends in other technology areas will make performance productivity one of the grand challenges in the future of computing. This talk will discuss technology trends for future computing and how these trends have created performance productivity challenges for developers. It will also provide a survey of researches that academia and industry have started to overcome these challenges.
Victor Lee received a B.S. in Electrical Engineering from University of Washington in 1994, an S.M. in Electrical Engineering and Computer Science from Massachusetts Institute of Technology in 1996. He joined Intel Corp. in 1997 where he worked on the Intel Pentium Pro, the Intel Pentium 4 processor, the Intel Itanium processor and the QPI interconnect architecture. He is also a key contributor to the Intel Many Integrated Core architecture and a member of the Intel Xeon Phi coprocessor design team. Victor is an IEEE senior member, a principal engineer and research scientist in Intel’s Parallel Computing Lab. His research interests include computer architecture, parallel algorithms and applications and auto-tuning.
Instructions for Final Papers
Papers are limited to 10 pages and must follow the LNCS style guides (linked below). All accepted papers will be included in the conference proceedings (electronic proceedings only), published by Springer in the LNCS series. Authors of accepted papers will be required to sign a Springer copyright form and submit all source documents of the paper (preferably as Latex files). At least one author of an accepted paper must register for and attend the workshop for inclusion in the proceedings.
A preliminary version of all accepted papers in Springer LNCS format (10 pages max.) is due on 7/30 (firm deadline). This version will be made available to attendees of the PROPER workshop. Please send these papers to the workshop chair (see below) by email.
Camera-ready revised versions of the workshop papers, which will be included in the official electronic proceesings, are due by the end of September 2013 and must also be in Springer LNCS format (10 pages max.). The final papers for the workshop proceedings will be collected via Easychair, which will be linkd from this page.
LNCS style guides:
Important Dates
Note: the deadlines are synchronized across all EuroPar workshops
- June 10th: submission deadline for full papers
- July 8th 9th: notification of acceptance
- July 31st: camera ready papers due
- July 20th: EuroPar early registration deadline
- July 30th: Preliminary papers due
- August 27th: PROPER workshop
- September 30th: final paper versions due for Springer proceedings
Program Committee:
- Martin Schulz, Lawrence Livermore National Laboratory (chair)
- Denis Barthou, INRIA
- David Böhme, German Research School for Simulation Sciences
- Karl Fürlinger, LMU München
- Michael Gerndt, TU München
- Kevin Huck, University of Oregon
- Koji Inoue, Kyushu University
- Andreas Knüpfer, TU Dresden
- Bettina Krammer, MoRitS, Bielefeld University & University of Applied Sciences Bielefeld
- Ignacio Laguna, Lawrence Livermore National Laboratory
- John Mellor-Crummey, Rice University
- Matthias Müller, RWTH Aachen
- Shirley Moore, University of Texas at El Paso
- Nathan Tallent, Pacific Northwest National Laboratory
- Jan Treibig, RRZE, Friedrich-Alexander-Universität Erlangen-Nürnberg
- Anh Vo, Microsoft
- Brian Wylie, Jülich Supercomputing Center
Contact
Martin Schulz
Lawrence Livermore National Laboratory (LLNL)
Center for Applied Scientific Computing (CASC)
Email schulzm@llnl.gov
